I2S configuration register 2
CAMERA_EN | Set this bit to enable camera mode. |
LCD_TX_WRX2_EN | LCD WR double for one datum. |
LCD_TX_SDX2_EN | Set this bit to duplicate data pairs (Frame Form 2) in LCD mode. |
DATA_ENABLE_TEST_EN | for debug camera mode enable |
DATA_ENABLE | for debug camera mode enable |
LCD_EN | Set this bit to enable LCD mode. |
EXT_ADC_START_EN | Set this bit to enable the function that ADC mode is triggered by external signal. |
INTER_VALID_EN | Set this bit to enable camera VGA reducing-resolution mode: only receive two consecutive cycle data in four consecutive clocks. |
CAM_SYNC_FIFO_RESET | Set this bit to reset FIFO in camera mode. |
CAM_CLK_LOOPBACK | Set this bit to loopback PCLK from I2S0I_WS_out. |
VSYNC_FILTER_EN | Set this bit to enable I2S VSYNC filter function. |
VSYNC_FILTER_THRES | Configure the I2S VSYNC filter threshold value. |