Espressif Systems /ESP32-S2 /I2S0 /CONF2

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Interpret as CONF2

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (CAMERA_EN)CAMERA_EN 0 (LCD_TX_WRX2_EN)LCD_TX_WRX2_EN 0 (LCD_TX_SDX2_EN)LCD_TX_SDX2_EN 0 (DATA_ENABLE_TEST_EN)DATA_ENABLE_TEST_EN 0 (DATA_ENABLE)DATA_ENABLE 0 (LCD_EN)LCD_EN 0 (EXT_ADC_START_EN)EXT_ADC_START_EN 0 (INTER_VALID_EN)INTER_VALID_EN 0 (CAM_SYNC_FIFO_RESET)CAM_SYNC_FIFO_RESET 0 (CAM_CLK_LOOPBACK)CAM_CLK_LOOPBACK 0 (VSYNC_FILTER_EN)VSYNC_FILTER_EN 0VSYNC_FILTER_THRES

Description

I2S configuration register 2

Fields

CAMERA_EN

Set this bit to enable camera mode.

LCD_TX_WRX2_EN

LCD WR double for one datum.

LCD_TX_SDX2_EN

Set this bit to duplicate data pairs (Frame Form 2) in LCD mode.

DATA_ENABLE_TEST_EN

for debug camera mode enable

DATA_ENABLE

for debug camera mode enable

LCD_EN

Set this bit to enable LCD mode.

EXT_ADC_START_EN

Set this bit to enable the function that ADC mode is triggered by external signal.

INTER_VALID_EN

Set this bit to enable camera VGA reducing-resolution mode: only receive two consecutive cycle data in four consecutive clocks.

CAM_SYNC_FIFO_RESET

Set this bit to reset FIFO in camera mode.

CAM_CLK_LOOPBACK

Set this bit to loopback PCLK from I2S0I_WS_out.

VSYNC_FILTER_EN

Set this bit to enable I2S VSYNC filter function.

VSYNC_FILTER_THRES

Configure the I2S VSYNC filter threshold value.

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